OrCAD / Allegro 17.4 QIR1 was released in early June 2020. It includes a variety of improvements for professional design of printed circuit boards. This includes usability improvements based on user feedback as well as a modernized look and feel of PCB Editor. System Capture will from now on read OrCAD Capture libraries and is plug compatible to the CIS library interface. In System Capture there is a reliability analysis without any models integrated. Users can try and use System Capture with any Allegro Schematic Entry license.These are the main new features:
In a schematic audit you can verify with 30+ rules the integrity of your schematic for net-connectivity, part-properties and component-values and cross-probe to instances and nets to fix warnings and errors. Electrical overstress analysis based just on the schematic verifies electrical stress for each device in the design and visualize stress reports with different derating. With schematic ERC basic connectivity checks are performed for schematic grammatic correctness.
Data is managed transparent to the user with “save”. User can optionally create “commit” points or add simple branching. Data management offers an intuitive rollback with preview of any version without opening. In a shared environment, previews are available via a browser. Data is indexed for analytics and search.
Entering the block level diagram in Allegro System Capture puts all information in one place and synchronized. In addition to Microsoft Visio or PowerPoint you can add interface specifications or organize the partitioning into multiple PCBs in one tool. If you want to reuse existing elements of previous designs you can do so by just importing the design and using the connector information. Allegro System Capture is creating a functional block diagram that can be linked to the detailed implementation.
Cadence and Intel* partnered to develop a constraint exchange solution for complex rules. Both developed an open, XML file format for providing executable constraints for Integrated Chips (CPU, SoC, PCH). Intel* will provide rule files through Intel Platform Design Studio (iPDS)* and Cadence Allegro Constraint Compiler will read the rule files and populate constraints in Constraint Manager for a design. Intel will provide rules for all new Intel components from iPDS starting with Tiger Lake* and Rocket Lake*.
* registered trademarks
Based on users feedback many areas of PCB Editor have been improved for easier usability and higher performance. In base release of 17.4 these areas were improved: shapes, slideVia, DRCs, move component, and show element. In QIR1 the improvement continued in these areas: backdrill, netrev / import logic, DFM checks, artwork generation, redraw, dynamic fillets, 3D canvas launch speed and 3D canvas memory consumption. Allegro PCB Editor supports now on user request also dark theme.
A new filter dialog allows switch on layers and objects to control visibility like in PCB Editor. This improves loading of large designs by only loading necessary objects. 3D canvas now has more information about net names, and properties. You can visualize an entire net or any object(s) of that net, busses, diff pairs, match groups, net classes, net groups, and XNets. You can export 3D folded view to Sigrity / Clarity to allow for accurate product level simulation / analysis for crosstalk or EMI simulation.
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