XJTAG DFT Assistant for OrCAD Capture

With free plugin, circuit board design software OrCAD Capture can display test coverage of the circuit in minutes. The plugin was developed by XJTAG, a provider of boundary scan hardware and software tools. This early testability information greatly simplifies a Design For Test, significantly reducing the number of subsequent changes.

Many contacts of integrated circuits, such as ball grid arrays (BGA), cannot be achieved with test needles, since the connections are located underneath the component and are sometimes laid only on inner layers in the printed circuit board. These connections can only be checked via JTAG or functional tests. However, many design guidelines require testing of all such wires. In the case of unreachable signals, a developer or PCB layouter must decide whether to award additional test points or to refrain from a test. The number of test points on printed circuit boards should be kept as low as possible in order to increase reliability and save space.

Here you can download the free XJTAG DFT Assistant for OrCAD Capture and install the plugin in OrCAD Capture. Afterwards, it is possible for the developer to generate a report about the test coverage for his circuit diagram in just a few minutes. With this graphic report, the developer can see which networks can be reached later in production via boundary scan test methods. All remaining nets are marked as untested in the report. Here, the developer can now specify on which networks he specifies a test point or which networks should remain untested.

This early information is very valuable because missing or too many test points are a common reason for redesign or costly engineering change orders (ECOs). The developer does not create a complete test program, but only uses the automatic functions of the plugin to find the non-JTAG networks to be tested. If it were first discovered in manufacturing that an important network, e.g. routed only on an inner layer or under components, then it requires a redesign of the layout to insert additional vias and recessed test areas in the resist.

Test points degrade the electrical properties of a design when they are removed from the network as stubs or vias, adversely affecting signal integrity and electromagnetic compatibility. Any unused or redundant test point takes up space on the surface of the circuit board and distances to components so that test needles can reach the test point. But space is precious when it comes to the miniaturization of electrical circuits.

The plugin requires no special knowledge of the developers on Boundary Scan test procedures. Once a netlist has been created, once all the ICs in the circuit are allocated, the freely available Boundary Scan information in form of BSDL files and utility pins used. Afterwards, the plugin can automatically build a scan chain and generate a report on test coverage without further user settings. Once mappings have been made, an update to a new netlist is available in seconds.

The plugin offers not only test coverage but also other useful information for the developer. The XJTAG Chain Checker identifies common JTAG chain setup or jamming issues, such as incorrectly connected or incorrectly terminated TAPs (Test Access Ports). That's another Design Rule Check for the JTAG bus in schematic, so to speak. The plugin supports the developer with best practices references to Design For Test.