Sigrity Simulation

Integrated with Cadence PCB and IC package design tools, the Sigrity solutions for signal integrity (SI) and power integrity (PI) provide advanced analysis both pre- and post-layout. Operating early in the design cycle allows for “what if” scenario exploration, sets more accurate design constraints, and reduces design iterations. Sigrity tools read directly to the Allegro PCB and IC package design database for fast and accurate integration of results. It provides a SPICE-based simulator and embedded field solvers for extraction of 2D and 3D structures. It supports transistor-level and behavioral I/O modeling, including power-aware simulation using IBIS models. Parallel bus and serial channel architecture can be explored pre-layout to compare alternatives, or post-layout for a comprehensive analysis of all associated signals.